Texas Instruments Speaker System TAS3002 User Manual

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Data  
Manual  
2001  
Digital Audio: Digital Speakers  
SLAS307B  
 
1 Introduction  
1.1 Description  
The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital  
parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides  
high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU  
2
2
through the I C slave port or from an external EEPROM through the I C master port.  
2
The TAS3002 device also has an integrated 24-bit stereo codec with two I C-selectable, single-ended inputs per  
channel.  
The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad  
filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass,  
high-pass, and low-pass).  
2
The internal loudness contour algorithm can be controlled and programmed with an I C command.  
2
Dynamic range compression/expansion (DRCE) is programmable through the I C port. The system designer can set  
the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.  
2
The TAS3002 device supports 13 serial interface formats (I S, left justified, right justified) with data word lengths of  
16, 18, 20, or 24 bits. The sampling frequency (f ) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface  
S
formats are listed and described in Section 2.1.  
The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock  
for the PLL is provided by an external master clock (MCLK) of 256f or 512f , or a 256f crystal.  
S
S
S
The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass,  
treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal  
microcontroller.  
1.2 Features  
Programmable seven-band parametric equalization  
Programmable digital volume control  
Programmable digital bass and treble control  
Programmable dynamic range compression/expansion (DRCE)  
Programmable loudness contour/dynamic bass control  
Configurable serial port for audio data  
Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of  
the codec (analog input). These channels are controlled by I C commands.  
2
Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume  
to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer  
channel. The output of the ADC is available for additional processing.  
Capability to digitally mix left and right input channels for a monaural output to facilitate subwoofer operation  
2
Serial I C master/slave port that allows:  
2
Downloading of control data to the device externally from the EEPROM or an I C master  
2
Controlling other I C devices  
1−1  
 
2
Two I C-selectable, single-ended analog input stereo channels  
Equalization bypass mode  
Single 3.3-V power supply  
Power down without reloading the coefficients  
Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz  
Master clock frequency of 256f or 512f  
S
S
Can have crystal input to replace MCLK. Crystal input frequency is 256f .  
S
Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters  
1.3 Functional Block Diagram  
Figure 1−1 is a block diagram showing the major functions of the TAS3002.  
1−2  
 
AINRP  
AINRM  
RINA  
Voltage  
Reference  
Analog  
Supplies  
Digital  
Supplies  
RINB  
AINRP  
AINRM  
24-Bit  
Stereo  
ADC  
SDOUT0  
AINLP  
AINLM  
LINA  
AINLP  
LINB  
AINLM  
VCOM  
ALLPASS  
INPA  
AOUTL  
AOUTR  
GPI5  
GPI4  
GPI3  
24-Bit  
Stereo DAC  
GPI2  
GPI1  
GPI0  
L+R  
L+R  
SDOUT2  
CS1  
SDA  
SCL  
32-Bit Audio Signal  
Processor  
SDOUT1  
32-Bit Audio Signal  
Processor  
PWR_DN  
RESET  
TEST  
L
R
SDATA  
Control  
OSC/CLK  
Select  
PLL  
Figure 1−1. TAS3002 Block Diagram  
1−3  
 
1.4 Terminal Assignments  
Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each  
terminal.  
PACKAGE  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
NC  
AV  
NC  
GPI5  
GPI4  
GPI3  
GPI2  
GPI1  
GPI0  
LINA  
RFILT  
1
2
3
4
5
6
7
8
9
V
DD  
AV  
SS(REF)  
AV  
SS  
INPA  
RESET  
CS1  
PWR_DN  
TEST  
ALLPASS  
SDOUT1  
SDOUT0  
CAP_PLL 10  
CLKSEL 11  
MCLKO 12  
13 14 15 16 17 18 19 20 21 22 23 24  
Figure 1−2. TAS3002 Terminal Assignments  
1.5 Terminal Functions  
Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type,  
and a description of the terminal function.  
Table 1−1. TAS3002 Terminal Functions  
TERMINAL  
I/O  
DESCRIPTION  
NAME  
AINLM  
NO.  
46  
47  
43  
42  
27  
39  
37  
35  
4
I
I
ADC left channel analog input (antialias capacitor)  
AINLP  
ADC left channel analog input (antialias capacitor)  
ADC right channel analog input (antialias capacitor)  
ADC right channel analog input (antialias capacitor)  
Logic high bypasses equalization filters  
Left channel analog output  
AINRM  
AINRP  
I
I
ALLPASS  
AOUTL  
AOUTR  
I
O
O
I
Right channel analog output  
AV  
AV  
AV  
Analog power supply (3.3 V)  
DD  
I
Analog voltage ground  
SS  
3
I
Analog ground voltage reference  
SS(REF)  
1−4  
 
Table 1−1. TAS3002 Terminal Functions (Continued)  
TERMINAL  
NAME  
I/O  
DESCRIPTION  
NO.  
10  
11  
7
CAP_PLL  
I
I
I
Loop filter for internal phase-locked loop (PLL)  
CLKSEL  
CS1  
Logic low selects 256f ; logic high selects 512f MCLK  
S
S
2
I C address bit A0; low = 68h, high = 6Ah  
Digital power supply (3.3 V)  
Digital ground  
DV  
DV  
17  
18  
I
I
I
DD  
SS  
GPI0  
GPI1  
GPI2  
GPI3  
GPI4  
GPI5  
28  
29  
30  
31  
32  
33  
Switch input terminals  
IFM/S  
INPA  
21  
5
I
O
I
Digital audio I/O control (low = input; high = output)  
Low when analog input A is selected (will sink 4 mA)  
Left channel analog input 1  
LINA  
1
LINB  
48  
19  
12  
34  
36  
8
I
Left channel analog input 2  
LRCLK/O  
MCLKO  
NC  
I/O  
O
Left/right clock input/output (output when IFM/S is high)  
MCLK output for slave devices  
No connection; Can be used as a printed circuit board routing channel  
No connection; Can be used as a printed circuit board routing channel  
Logic high places the TAS3002 device in power-down mode  
Logic low resets the TAS3002 device to the initial state  
Right channel analog input 1  
NC  
PWR_DN  
RESET  
RINA  
I
I
6
40  
41  
15  
20  
16  
22  
23  
25  
26  
24  
9
I
RINB  
I
Right channel analog input 2  
2
SCL  
I/O  
I/O  
I/O  
I
I C clock connection  
SCLK/O  
SDA  
Shift (bit) clock input (output when IFM/S is high)  
2
I C data connection  
SDIN1  
SDIN2  
SDOUT0  
SDOUT1  
SDOUT2  
TEST  
Serial data input 1  
I
Serial data input 2  
O
O
O
I
Serial data output from ADC  
Serial data output (from internal audio processing)  
Serial data output (a monaural mix of left and right, before processing)  
Reserved manufacturing test terminal; connect to DV  
SS  
VCOM  
38  
O
Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-µF and 0.1-µF  
capacitors)  
V
V
V
45  
44  
2
I
I
ADC minus voltage reference  
REFM  
REFP  
RFILT  
ADC plus voltage reference  
O
I
Voltage reference low pass filter  
XTALI/MCLK  
XTALO  
13  
14  
Crystal or external MCLK input  
I
Crystal input (crystal is connected between terminals 13 and 14)  
1−5  
 
1−6  
 
2 Audio Data Formats  
2.1 Serial Interface Formats  
The TAS3002 device works in master or slave mode.  
In the master mode, terminal 21 (IFM/S) is tied high. This activates the master clock (MCLK) circuitry. A crystal can  
be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be  
connected to XTALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and  
20 (SCLK/O) becoming outputs to drive slave devices.  
In the slave mode, IFM/S is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device  
requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options  
for selecting the clock rates. If the 512f MCLK rate is selected, terminal 11 (CLKSEL) is tied high and an MCLK rate  
S
of 512f must be supplied. If the 256f MCLK is selected, CLKSEL is tied low and an MCLK of 256f must be supplied.  
S
S
S
In both cases, an LRCLK of 64SCLK must be supplied.  
MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.  
If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.  
2
The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I S, right justified,  
and left justified. Table 2−1 indicates how the 13 options are selected using the I C bus and the main control register  
(MCR, I C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64f .  
Additionally, the 16-bit mode operates at 32f .  
2
2
S
S
Table 2−1. Serial Interface Options  
SERIAL INTERFACE  
SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0  
MODE  
MCR BIT (6)  
MCR BIT (5−4)  
MCR BIT (1−0)  
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
00  
00  
01  
10  
00  
01  
10  
00  
01  
10  
00  
01  
10  
00  
00  
00  
00  
01  
01  
01  
10  
10  
10  
11  
11  
11  
16-bit, 32f  
S
16-bit, left justified, 64f  
S
2
16-bit, right justified, 64f  
S
S
S
S
2
3
16-bit, I S, 64f  
S
4
18-bit, left justified, 64f  
S
5
18-bit, right justified, 64f  
2
6
18-bit, I S, 64f  
S
7
20-bit, left justified, 64f  
S
8
20-bit, right justified, 64f  
2
9
20-bit, I S, 64f  
S
10  
11  
12  
24-bit, left justified, 64f  
S
24-bit, right justified, 64f  
2
24-bit, I S, 64f  
S
Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the  
different interface protocols.  
2−1  
 
2.2 Digital Output Modes  
The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.  
2.2.1 MSB-First, Right-Justified, Serial-Interface Format  
The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1  
shows the following characteristics of this protocol:  
Left channel is transmitted when LRCLK is high.  
The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.  
The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the  
next rising edge of SCLK.  
If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.  
SCLK  
LRCLK = f  
S
SDIN  
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
LSB  
LSB  
… …  
… …  
… …  
… …  
… …  
… …  
… …  
… …  
SDOUT  
Left Channel  
Right Channel  
Figure 2−1. MSB-First, Right-Justified, Serial-Interface Format  
2−2  
 
2
2.2.2 I S Serial-Interface Format  
2
The normal output mode for the I S serial-interface format is for 16, 18, 20, or 24 bits.  
Figure 2−2 shows the following characteristics of this protocol:  
Left channel is transmitted when LRCLK is low.  
SDIN is sampled with the rising edge of SCLK.  
SDOUT is transmitted on the falling edge of SCLK.  
If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.  
SCLK  
LRCLK = f  
S
SDIN  
X
X
MSB  
MSB  
LSB  
LSB  
X
X
MSB  
MSB  
LSB  
LSB  
… …  
… …  
… …  
… …  
SDOUT  
Left Channel  
2
Right Channel  
Figure 2−2. I S Serial-Interface Format  
2−3  
 
2.2.3 MSB-Left-Justified, Serial-Interface Format  
The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits.  
Figure 2−3 shows the following characteristics of this protocol:  
Left channel is transmitted when LRCLK is high.  
The SDIN data is justified to the leading edge of the LRCLK.  
The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.  
SCLK  
LRCLK = f  
S
MSB  
MSB  
LSB  
LSB  
MSB  
MSB  
LSB  
LSB  
SDIN  
… …  
… …  
… …  
… …  
… …  
… …  
… …  
… …  
SDOUT  
Left Channel  
Right Channel  
Figure 2−3. MSB-Left-Justified, Serial-Interface Format  
2−4  
 
2.3 Switching Characteristics  
PARAMETER  
MIN  
325.5  
20  
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
f
SCLK cycle time  
c(SCLK)  
SCLK rising to LRCLK edge  
SDOUT valid from SCLK falling edge (see Note 1)  
SDIN setup before SCLK rising edge  
SDIN hold after SCLK rising edge  
LRCLK frequency  
ns  
d(SLR)  
(1/256f ) + 10  
S
ns  
d(SDOUT)  
su(SDIN)  
h(SDIN)  
(LRCLK)  
20  
100  
32  
ns  
ns  
44.1  
50  
48  
kHz  
%
Duty cycle  
NOTE 1: Maximum of 50-pF external load on SDOUT.  
t
c(SCLK)  
t
r(SCLK)  
SCLK  
t
f(SCLK)  
t
d(SLR)  
LRCLK  
t
t
d(SLR)  
d(SDOUT)  
SDOUT1  
SDOUT2  
SDOUT0  
t
su(SDIN)  
t
h(SDIN)  
SDIN1  
SDIN2  
2
Figure 2−4. For Right-/Left-Justified and I S Serial Protocols  
2−5  
 
2−6  
 
3 Analog Input/Output  
The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or  
2
B analog input is accomplished by setting a bit in the analog control register (ACR) by an I C command. Additionally,  
the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC).  
3.1 Analog Input  
Figure 3−1 shows the technique and components required for analog input to the TAS3002 device. The maximum  
input signal must not exceed 0.7 V . Selection of the above component values gives a frequency response from  
rms  
20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems.  
2
1200 pF  
AINRP  
AINRM  
0.47 µF  
RINA  
Voltage  
Reference  
1
RINB  
1
0.47 µF  
AINRP  
2
AINRM  
24-Bit  
1200 pF  
AINLP  
Stereo  
ADC  
AINLM  
LINA  
0.47 µF  
1
LINB  
AINLP  
1
0.47 µF  
AINLM  
1
2
3
Analog Inputs − Use 0.47 µF for 20-Hz Cutoff  
Anti-Alias Capacitors for f = 48 kHz  
Input Select Command  
From Internal Controller  
S
Tie unused analog inputs to analog ground through 0.1-µF capacitors.  
Figure 3−1. Analog Input to the TAS3002 Device  
3.2 Analog Output  
3.2.1 Direct Analog Output  
The full scale analog output from the TAS3002 device is 0.707 V . It is referenced to VCOM which is approximately  
rms  
1.5 Vdc. VCOM must be decoupled with the network shown in Figure 3−2.  
3−1  
 
Analog Output  
(Adjust Capacitors for Desired  
Low Frequency Response)  
AOUTR  
VCOM  
24-Bit  
DAC  
+
0.1 µF  
10 µF  
AOUTL  
AGND  
Figure 3−2. VCOM Decoupling Network  
3.2.2 Analog Output With Gain  
Because the maximum analog output from the TAS3002 device is 0.707 V , the output level can be increased by  
rms  
using an external amplifier. The circuit shown in Figure 3−3 boosts the output level to 1 V  
(when it has a gain of  
rms  
1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers the noise floor, THD + N is  
improved also.  
C4  
Analog Output  
(Adjust Capacitors for Desired  
Low Frequency Response)  
AOUTR  
C1  
+
TLV2362  
C3  
or Equilvalent  
VCOM  
24-Bit  
DAC  
+
10 µF  
0.1 µF  
+5 Op Amp/2  
AOUTL  
C5  
AGND  
C2  
C
= C = C  
3
1
2
+
C
= C  
5
4
TLV2362  
or Equilvalent  
+5 Op Amp/2  
Figure 3−3. Analog Output With External Amplifier  
3−2  
 
3.2.3 Reference Voltage Filter  
Figure 3−4 shows the TAS3002 reference voltage filter.  
0.1 µF  
15 µF  
1 µF  
+
+
0.1 µF  
0.1 µF  
4
3
2
45  
V
REFP  
44  
TAS3002  
Figure 3−4. TAS3002 Reference Voltage Filter  
3−3  
 
3−4  
 
4 Audio Control/Enhancement Functions  
4.1 Soft Volume Update  
The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and  
pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute).  
2
The volume is adjustable by downloading a gain coefficient through the I C interface in 4.16 format—4 bits for the  
integer and 16 bits for the fractional part. NO TAG lists the 4.16 coefficients converted into dB for the range of 70  
dB to 18 dB with 0.5-dB step resolution.  
Right and left channel volumes can be unganged and set to different values. This feature implements a balance  
control.  
Volume is changed by writing the desired value into the volume control registers. This is done by asserting the  
volume-up or volume-down GPI terminal (see Section 7.6.1) for a limited range of volume control. Alternatively,  
2
volume control settings can be sent to the TAS3002 device over the I C bus.  
4.2 Software Soft Mute  
Soft mute is implemented by loading all zeros in the volume control register. This causes the volume to ramp down  
over a duration of 2048f samples to a final output of 0 (− infinity dB).  
S
Soft mute can be enabled by either asserting the mute GPI terminal (see Section 7.6.1) or sending a mute command  
2
over the I C bus. Subsequent assertions of the mute GPI terminal toggle soft mute off and on.  
4.3 Input Mixer Control  
The TAS3002 device is capable of mixing and multiplexing three channels (SDIN1, SDIN2, and the ADC output) of  
serial audio data. The mixing is controlled through three mixer control registers. This is accomplished by loading  
values into the corresponding bytes of the mixer left gain (07h) and mixer right gain (08h) control registers. See  
Figure 4−1 for a functional block diagram of the input mixer.  
The values loaded into these registers are in 4.20 format—4 bits for the integer and 20 bits for the fractional part.  
NO TAG lists the 4.20 numbers converted into dB for the range of 70 dB to 18 dB, although any positive 4.20 number  
may be used.  
To mute any of the channels, 0s are loaded into the respective mixer control register.  
Mixer controls are updated instantly and can cause audible artifacts for large changes in setting when updated  
dynamically outside of the fast load mode; therefore, it is desirable to use fast load in conjunction with the soft-volume  
mode.  
SDIN1, SDIN2, and the ADC output can be mixed with a user-selectable gain for each channel. The gain control  
registers are represented in 4.20 format.  
4−1  
 
Left Channel Mix Coefficients  
I C Register Address 08h  
SDIN1 ^ SDIN2 ^ ADC  
2
= (3) 24-Bit Left Mix Coefficient  
SDIN1_L  
SDIN2_L  
ADC_L  
Soft  
Volume  
DRCE  
L_SUM  
7 Biquad  
Filters  
Tone  
SDOUT1  
SDIN1_R  
SDIN2_R  
ADC_R  
Soft  
Volume  
DRCE  
7 Biquad  
Filters  
Tone  
R_SUM  
1/2  
SDOUT2  
L + R_SUM  
1/2  
Right Channel Mix Coefficients  
I C Register Address 07h  
SDIN1 ^ SDIN2 ^ ADC  
= (3) 24-Bit Right Mix Coefficient  
2
Figure 4−1. TAS3002 Mixer Function  
4.4 Mono Mixer Control  
The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio  
data from the input mixer in order to derive a monaural channel. This mixer has a fixed gain of −6 dB so that full scale  
inputs on L_sum and R_sum do not produce clipping on the resulting L+R_sum.  
The output of this mixer is present on terminal 24 (SDOUT2) and is generally used for a digitally-mixed subwoofer  
or center channel application.  
4.5 Treble Control  
The treble gain level may be adjusted within the range of 15 dB to 15 dB with 0.5-dB step resolution. The level  
changes are accomplished by downloading treble codes (shown in NO TAG) into the treble gain register.  
Alternatively, a limited range of treble control is available by asserting the treble-up or treble-down GPI terminal (see  
Section 7.6.1).  
The treble control has a corner frequency of 6 kHz at a 48-kHz sample rate.  
The gain values for treble control can be found in Section NO TAG.  
4−2  
 
4.6 Bass Control  
The bass gain level can be adjusted within the range of 15 dB to 15 dB with 0.5-dB step resolution. The level changes  
are accomplished by downloading bass codes (shown in NO TAG) into the bass frequency control register.  
Alternatively, a limited range of bass control is available by asserting the bass-up or bass-down GPI terminal (see  
Section 7.6.1).  
Bass control is a shelf filter with a corner frequency of 250 Hz at a 48-kHz sample rate.  
The gain values for bass control can be found in Section NO TAG.  
4.7 De-Emphasis Mode (DM)  
De-emphasis is implemented in the DAC and is software controlled. De-emphasis is valid at 44.1 kHz and 48 kHz.  
2
To enable de-emphasis, values are written into the analog control register via the I C command. See Section 4.8 for  
analog control register operation.  
Figure 4−2 illustrates the frequency response of the de-emphasis mode.  
De-Emphasis  
Response (dB)  
3.18  
10.6  
(50 µs)  
(15 µs)  
Frequency (kHz)  
Figure 4−2. De-Emphasis Mode Frequency Response  
4−3  
 
4.8 Analog Control Register (40h)  
The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC,  
and analog power down.  
2
An I C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h.  
Bit  
7
R/W  
0
6
R/W  
0
5
R/W  
0
4
R/W  
0
3
R/W  
0
2
R/W  
0
1
R/W  
0
0
R/W  
0
Type  
Default  
Table 4−1. Analog Control Register Description  
BIT  
FIELD NAME  
TYPE  
DESCRIPTION  
7
Reserved  
R/W  
Reset to 0  
6
Reserved  
R/W  
Reset to 0  
5−4  
3−2  
Reserved  
DM(1−0)  
R/W  
R/W  
Reserved. Bits 5 and 4 return 0s when read.  
De-emphasis control  
00 = De-emphasis off (initial condition after reset)  
01 = 48 kHz sample rate de-emphasis selected  
10 = 44.1 kHz sample rate de-emphasis selected  
11 = Reserved  
1
0
INP  
R/W  
R/W  
Analog input select  
0 = LINA and RINA selected (initial condition after reset)  
1 = LINB and RINB selected  
APD  
Analog power down  
0 = Normal operation (initial condition after reset)  
1 = Power down  
4−4  
 
4.9 Dynamic Loudness Contour  
The necessity for applying loudness compensation to playback systems to compensate for the fact that the ear  
perceives bass and treble less audibly at low levels than at high ones has been established since the first data was  
published by Fletcher and Munson in 1933.  
There are many equal-loudness contours in publication, like Steven’s contours, Robinson and Dadson contours.  
Some have even reached the acceptance level of ISO recommendation.  
The TAS3002 device has a simplified loudness contour algorithm that diminishes the effect of weak bass at low  
listening levels. Since contour has volume level dependency, the user must define the relation between the gain of  
the contour circuit and the volume level.  
Figure 4−3 is a block diagram of this circuit.  
Volume  
Biquad  
Gain  
Figure 4−3. Dynamic Loudness Contour Block Diagram  
2
The loudness contour is activated by sending an activation command via I C from an external device. Optionally, a  
contour gain command can be sent by an external device to provide tracking with the system volume control.  
4.9.1 Loudness Biquads  
2
Loudness biquad filters for the left and right channels are independently programmable via I C. Their subaddresses  
are 21h and 22h, respectively. The digital filters are written as five 24-bit (4.20) hex coefficients for each channel.  
4.9.2 Loudness Gain  
2
Loudness gain values for the left and right channels are independently programmable via I C. Their subaddresses  
are 23h and 24h, respectively. The gain values are written as one 4.20 hex coefficient for each channel.  
4.9.3 Loudness Contour Operation  
When the frequency of the loudness contour is determined, a digital filter must be developed. Then, the gain of the  
filter is determined. These values are placed in the storage area of the system controller (microcontroller) and sent  
to the TAS3002 device when it is desired to activate the loudness contour.  
If it is necessary to change the frequency or gain of the contour, new gain and filter coefficients are sent by the system  
controller. This function is performed normally when the volume control is changed (that is, more volume, less  
contour). The gain of the loudness contour filter then tracks the volume control.  
The loudness contour biquad filters are provided in addition to the seven equalization biquad filters.  
See Section NO TAG for programming instructions.  
4−5  
 
4.10 Dynamic Range Compression/Expansion (DRCE)  
The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCE  
receives data, and affects scaling after the volume/loudness block. As shown in Figure 4−4, the DRCE is applied after  
the volume/loudness control block as a DRCE scale factor. The DRCE must be adjusted such that the signal does  
not reach the hard limit value. However, if the signal does reach the maximum digital value, the saturation logic serves  
as a hard limiter that does not allow the signal to extend beyond the available range.  
Loudness  
(Parametric  
Equalization)  
(Left Channel Mixer)  
(Tone)  
(DRCE Scaling)  
SDIN1_L  
SDIN2_L  
(7)  
Order  
IIR Filters  
LEFT_SUM  
LEFT_OUT  
Bass/  
Treble  
Soft  
Volume/  
Saturation  
Logic  
nd  
2
ANALOGIN_L  
Dynamic  
Range  
(Analog in From ADC)  
Control  
ANALOGIN_R  
SDIN1_R  
RIGHT_SUM  
(7)  
Order  
IIR Filters  
RIGHT_OUT  
Bass/  
Treble  
Soft  
Volume/  
Saturation  
Logic  
nd  
2
SDIN2_R  
(Right Channel Mixer)  
(DRCE Scaling)  
(Parametric  
(Tone)  
Equalization)  
Loudness  
Figure 4−4. TAS3002 Digital Signal Processing Block Diagram  
The DRCE instruction consists of eight bytes that must be sent each time in the order shown in the example code  
of NO TAG. Each instruction downloaded must be eight bytes. If only one byte is changed, all eight bytes must be  
transmitted. The first two bytes remain the same for every instruction, however the last six bytes can be programmed  
using hexadecimal values from the corresponding tables referred to in Section NO TAG.  
With high compression ratios and fast attack times available, this function is suited for a commercial killer in a  
television set application.  
4.11 AllPass Function  
This function is enabled by setting terminal 27 (ALLPASS) on the TAS3002 device to 1. When asserted, the internal  
equalization filters are set into AllPass (flat) mode. When this terminal is reset to 0, the equalization filters are returned  
to the equalization that was in use before the terminal was asserted.  
In AllPass mode, the bass and treble controls are still functional.  
This function is frequently used for headphones. When the headphone plug is inserted into its jack, a switched contact  
in the jack enables the AllPass function.  
The AllPass function also can be activated by writing a 1 to bit 2 of the analog control register.  
4−6  
 
4.12 Main Control Register 1 (01h)  
The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2  
(MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, and  
2
serial-port word length. It is accessed via I C with the address 01h.  
MCR1 (01h)  
Bit  
b7  
R/W  
1
b6  
R/W  
X
b5  
R/W  
X
b4  
R/W  
X
b3  
R
b2  
R
b1  
R/W  
X
b0  
R/W  
X
Type  
Default  
X
X
Table 4−2. Main Control Register 1 Description  
FIELD NAME  
BIT  
TYPE  
DESCRIPTION  
7
FL  
R/W  
R/W  
R/W  
Fast load  
0 = Normal operation mode  
1 = Fast -load mode (default)  
6
SC  
E
SCLK frequency  
0 = SCLK is 32 f .  
1 = SCLK is 64 f .  
S
S
5−4  
Serial port mode  
00 = Left justified  
01 = Right justified  
2
10 = I S  
11 = Reserved  
3−2  
1−0  
Reserved  
W
R
Reserved  
R/W  
Serial port word length  
00 = 16-bit  
01 = 18-bit  
10 = 20-bit  
11 = 24-bit  
4.13 Main Control Register 2 (43h)  
The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2  
(MCR2). The MCR2 register contains the bits associated with the AllPass function and the download of bass and  
2
treble control information, and it is accessed via I C with the address 43h.  
MCR2 (43h)  
Bit  
7
R/W  
0
6
R
0
5
R
0
4
R
x
3
R
x
2
R
x
1
R/W  
0
0
R
0
Type  
Default  
Table 4−3. Main Control Register 2 Description  
FIELD NAME  
BIT  
TYPE  
DESCRIPTION  
7
Reserved  
R/W  
0 = Normal operation (initial condition after reset)  
1 = Download bass and treble  
6−5  
4−2  
1
Reserved  
Reserved  
DM(1−0)  
R
R
Reserved. Bits 6 and 5 return 0s when read.  
Undefined.  
R/W  
0 = Normal operation (initial condition after reset)  
1 = AllPass mode (bass and treble are still functional)  
0
INP  
R
Reserved. Bit 0 returns 0 when read.  
4−7  
 
4−8  
 
5 Filter Processor  
5.1 Biquad Block  
The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown in  
Figure 5−1. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel has  
independent coefficients.  
Biquad 0  
Biquad 1 ...  
Biquad 6  
Figure 5−1. Biquad Cascade Configuration  
5.1.1 Filter Coefficients  
2
The filter coefficients for the TAS3002 device are downloaded through the I C port and loaded into the biquad memory  
space. Each biquad filter memory space has an independent address. Digital audio data coming into the device is  
processed by the biquad block and then converted into analog waveforms by the DAC. Alternatively, filters can be  
loaded by asserting terminals on the GPI port.  
5.1.2 Biquad Structure  
The biquad structure that is used for the parametric equalization filters is as follows:  
*1  
*2  
b ) b z  
) b z  
0
1
2
H(z) +  
*1  
*2  
a ) a z  
) a z  
0
1
2
(1)  
NOTE: a is fixed at value 1 and is not downloadable.  
0
The coefficients for these filters are represented in 4.20 format—4 bits for the integer part and 20 bits for the fractional  
2
part. In order to transmit them over I C, it is necessary to separate each coefficient into three bytes. The upper 4 bits  
of byte 2 comprise the integer part; the lower 4 bytes of byte 2 plus byte 1 and byte 0 comprise the fractional part.  
The filters can be designed using the automatic loudspeaker equalization program (ALE) or a script running under  
MatLab named Filtermaker. Both of these tools are available from Texas Instruments.  
5−1  
 
5−2  
 
2
6 I C Serial Control Interface  
6.1 Introduction  
2
Control parameters for the TAS3002 device can be loaded from an I C serial EEPROM by using the TAS3002 master  
2
interface mode. If no EEPROM is found, the TAS3002 device becomes a slave device and loads from another I C  
master interface. Information loaded into the TAS3002 registers is defined in Appendix A.  
2
The I C bus uses terminals 16 (SDA for data) and 15 (SCL for clock) to communicate between integrated circuits in  
a system. These devices can be addressed by sending a unique 7-bit slave address plus R/W bit (1 byte). All  
compatible devices share the same terminals via a bidirectional bus using a wired-AND connection. An external  
pullup resistor must be used to set the high level on the bus. The TAS3002 device operates in standard mode up to  
100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF.  
Furthermore, the TAS3002 device supports a subset of the SMBus protocol. When it is attached to the SMBus, then  
byte, word, and block transfers are supported. The SMBus NAK function is not supported and care must be taken  
with the sequence of the instructions sent to the TAS3002 device.  
Additionally, the TAS3002 device operates in either master or slave mode; therefore, at least one device connected  
2
to the I C bus must operate in master mode.  
2
6.2 I C Protocol  
The bus standard uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low  
transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur  
within the low time of the clock period. Figure 6−1 shows these conditions. These start and stop conditions for the  
2
I C bus are required by standard protocol to be generated by the master. The master must also generate the 7-bit  
slave address and the read/write (R/W) bit to open communication with another device and then wait for an  
acknowledge condition. The slave holds SDA low during acknowledge clock period to indicate an acknowledgment.  
When this occurs, the master transmits the next byte of the sequence.  
After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the  
number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master  
generates a stop condition to release the bus. Figure 6−1 shows a generic data transfer sequence.  
7-Bit  
Slave Address  
R/  
W
8-Bit Register Data  
for Address (N)  
8-Bit Register Data  
for Address (N+1)  
8-Bit Register Data  
for Address (N+2)  
A
A
A
A
SDA  
7
6
1
0
7
6
1
0
7
6
1
0
7
6
1
0
SCL  
Start  
Stop  
2
Figure 6−1. Typical I C Data Transfer Sequence  
6−1  
 
2
Table 6−1 lists the definitions used by the I C protocol.  
2
Table 6−1. I C Protocol Definitions  
DEFINITION  
Transmitter  
DESCRIPTION  
The device that sends data  
Receiver  
The device that receives data  
Master  
The device that initiates a transfer, generates clock signals, and terminates the transfer  
The device addressed by the master  
Slave  
Multimaster  
Arbitration  
Synchronization  
More than one master can attempt to control the bus at the same time without corrupting the message.  
Procedure to ensure the message is not corrupted when two masters attempt to control the bus.  
Procedure to synchronize the clock signals of two or more devices  
6.3 Operation  
The 7-bit address for the TAS3002 device is 0110 10X R/W where X is a programmable address bit, set by terminal 7  
2
(CS1). Combining CS1 and the R/W bit, the TAS3002 device can respond to four different I C addresses (two read  
2
2
and two write). These two addresses are licensed I C addresses that do not conflict with other licensed I C audio  
devices. In addition to the 7-bit device address, subaddresses direct communication to the proper memory location  
within the device. A complete table of subaddresses and control registers is provided in Appendix A. For example,  
2
to change bass to 10-dB gain, Section 6.3.1 shows the data that is written to the I C port:  
2
Table 6−2. I C Address Byte Table  
2
I C ADDRESS BYTE  
A6A1  
011010  
011010  
011010  
011010  
CS1 (A0)  
R/W  
68h  
69h  
6Ah  
6Bh  
0
0
1
1
0
1
0
1
6.3.1 Write Cycle Example  
Start  
Slave Address  
R/W  
A
Subaddress  
A
Data  
A
Stop  
FUNCTION  
DESCRIPTION  
2
Start  
Start condition as defined in I C  
0110100 (CS1 = 0)  
0 (write)  
Slave address  
R/W  
A
2
Acknowledgement as defined in I C (slave)  
Subaddress (treble control register)  
0000 0101  
0111 0010  
Data (0 dB gain)  
Stop  
2
Stop condition as defined in I C  
NOTE: Table is for serial data (SDA); serial clock (SCL) is not shown but conditions apply as well.  
Whenever writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle.  
For example, if the volume control register with subaddress 04h is written to, six bytes of data must follow; otherwise,  
the cycle is incomplete and errors occur.  
6−2  
 
2
6.3.2 TAS3002 I C Readback Example  
2
The TAS3002 saves in a stack or first-in first-out (FIFO) buffer the last 7 bytes that were sent to it. When an I C read  
command is sent to the device (LSB=high), it answers by popping the first byte off the stack. The TAS3002 then  
2
expects either a Send Ack command or an I C Stop command from the host. If a Send Ack command is sent from  
2
the host then the TAS3002 pops another byte off the stack. If an I C Stop is sent then the TAS3002 ends this  
transaction. The proper sequence for reading is described as follows:  
2
I C Start  
2
Send I C address byte with read bit set to 1 (LSB set equal to 1)  
Receive Byte 0  
Send Ack  
Receive Byte 1  
Send Ack  
Receive Byte 2  
Send Ack  
Receive Byte 3  
Send Ack  
Receive Byte 4  
Send Ack  
Receive Byte 5  
Send Ack  
Receive Byte 6 (if an ACK is sent after byte 6 it locks up the TAS3002)  
2
I C Stop  
Where:  
2
2
I C Start is a valid I C Start command.  
2
Receive Byte is a valid I C command which reads a byte from the TAS3002.  
2
Send Ack is a a valid I C command that informs the TAS3002 that a byte has been read.  
2
2
I C Stop is a valid I C Stop command.  
2
NOTES: 1. The TAS3002 will appear to be locked up, if a Send Ack is issued after the last byte read. It is required to send an I C Stop command  
after the last byte and not a Send Ack.  
2
2
2
2
2. The I C Start and I C Stop commands are the same for both I C read and I C write.  
2
6.3.3 I C Wait States  
The TAS3002 device performs interpolation algorithms for its volume and tone controls. If a volume or tone change  
2
2
is sent to the part via I C, the command sent after the volume or tone (bass and treble) change causes an I C wait  
state to occur. This wait state lasts from 41 ms to 231 ms, depending on the system clock rate, the command sent,  
and, in the case of bass or treble, the amount of the change.  
Secondly, if a long series of commands is sent to the TAS3002 device, it may occasionally create a short wait state  
on the order of 150 µs to 300 µs while it loads and processes the commands.  
When a sample rate of 32 kHz is used, longer wait states can occur, occasionally up to 15 ms.  
2
The preferred way to take care of wait states is to use an I C controller that recognizes wait states. During the wait  
2
state period, it stops sending data over I C. If this function is not available on the system controller, fixed delays can  
be implemented in the system software to ensure that the controller is not trying to send more data while the TAS3002  
2
device is busy. Sending I C data while the TAS3002 device is busy causes errors and locks up the device, which must  
then be reset.  
6−3  
 
Table 6−3 gives typical values of the wait states that can be expected with the various functions of the part:  
2
Table 6−3. I C Wait States  
SYSTEM SAMPLING FREQUENCY  
Comment  
Not dependent on size of change  
0 to −18 dB  
32 kHz  
62 ms  
231 ms  
231 ms  
300 µs  
None  
44.1 kHz  
49 ms  
48 kHz  
41 ms  
153 ms  
153 ms  
300 µs  
None  
Volume  
Bass  
167 ms  
167 ms  
300 µs  
None  
Treble  
0 to −18 dB  
DRC on  
Mixer  
Loudness  
Equalization  
None  
None  
None  
15 ms  
190 µs  
300 µs  
Can occur with each filter  
6.4 SMBus Operation  
The TAS3002 device supports a subset of the SMBus protocol. With proper programming techniques, it is possible  
to use the SMBus to set up the TAS3002 device.  
6.4.1 Block Write Protocol  
The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block. To send a  
command using this format, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the  
subaddress (also with MSB set high) must be programmed into the SMBus command byte. This operation signals  
the TAS3002 device that the next byte is the SMBus byte-count byte. The next byte after the byte count is then entered  
into the device as the first byte of data.  
SMBus  
Command Byte  
68h  
8rh  
xx  
dd  
dd  
dd  
TAS3002  
Address  
Subaddress  
(r = subaddress)  
Byte Count  
(Don’t Care)  
Data  
Data  
Data  
6.4.2 Write Byte Protocol  
The TAS3002 device also supports the SMBus write byte protocol. Writing to the main control register (MCR), bass,  
and treble registers requires using the byte write protocol. To send a command using this protocol, the most significant  
bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be  
programmed into the SMBus command byte. The next byte after the command byte is then entered into the device  
as the first byte of data.  
SMBus  
Command Byte  
68h  
8rh  
dd  
TAS3002  
Address  
Subaddress  
(r = subaddress)  
Data  
6−4  
 
6.4.3 Wait States  
2
If separate I C/SMBus commands are sent too frequently, the TAS3002 device can generate a bus wait state. This  
happens when the device is busy while performing smoothing operations and changing volume, bass, and treble.  
The wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowable time allowed  
according to the SMBus specification (worst case 200 ms).  
The following is a possible bus wait state scenario:  
CODE  
Start  
Start  
68  
68  
84  
84  
06  
06  
01  
01  
00  
00  
00  
01  
00  
00  
01  
00  
00  
Stop  
00  
ACTUAL  
Wait  
Stop  
2
If the master does not recognize bus waiting or if the master times out on a long wait, the master must not send consecutive I C/SMBus commands  
without a time interval of 200 ms between transactions.  
6.4.4 TAS3002 SMBus Readback  
The TAS3002 device supports a subset of SMBus readback. When an SMBus read command is sent to the device  
(LSB = high), it answers with the subaddress and the last six bytes written.  
SMBus  
Command  
Byte  
Byte  
Count  
SENT  
Start  
Start  
69h  
07h  
xxh  
aah  
07h  
ddh  
Stop  
ddh  
RECEIVED  
ddh  
ddh  
ddh  
ddh  
Stop  
Byte  
Count  
Where:  
xxh = Command byte. It is a don’t care because the response contains only the subaddress and the  
last six bytes of data written to the TAS3002 device.  
aah = The last subaddress accessed in the device  
ddh = Data bytes from the TAS3002 device  
NOTE: Use read sequence defined in 6.3.2  
6−5  
 
6−6  
 
7 Microcontroller Operation  
The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform  
2
housekeeping and interface functions. Additionally, it handles I C communication and general purpose input  
functions.  
7.1 General Description  
The microcontroller uses a 256f system clock and can access up to 8K bytes of memory. It interfaces with the digital  
S
2
audio interface I C master/slave for downloading data and coefficients. It also interfaces with two internal DSPs for  
transferring coefficients and other information.  
2
The TAS3002 coefficients are loaded through I C in the master or slave mode. Standard audio processing functions  
(volume, bass, and treble) can be controlled/activated through external switches connected to the six GPI terminals.  
Upon reset, the internal microcontroller sets all coefficients and audio parameters to the default values. See  
Section 7.2.2 for default values.  
If the TAS3002 address is 68h (ADDR_SEL=0), it becomes the bus master device and attempts to load parameters  
and coefficients from the external EEPROM. If no EEPROM is present, the TAS3002 device remains in its default  
2
condition. If addresses other than 68h/69h are set, the TAS3002 device only operates as an I C slave device.  
2
If the microcontroller determines the TAS3002 device has an I C address of 68h/69h and the EEPROM is present,  
the microcontroller downloads coefficients from the EEPROM. Once the download is complete, it enables the serial  
2
audio in the mode defined by an I C write to the MCR to transfer data into and out of the device. Before reading the  
2
EEPROM, the serial audio port defaults to I S mode.  
2
The TAS3002 device allows the user to update volume, bass, and treble dynamically by an I C slave command or  
by a simple GPI input. The GPI can select volume up and down, bass/treble up and down, or digital equalizations.  
Up to five different equalizations (that is, flat, jazz, rock, voice, etc.) can be stored in the external EEPROM. Also,  
2
DRCE, MCR1, MCR2, and loudness contour are enabled and disabled by I C.  
2
2
When the TAS3002 device operates in the I C master mode, it echoes changes to all of its functions to other I C  
addresses that are defined in its external EEPROM. If no addresses are defined, it does not echo.  
7.2 Power-Up/Power-Down Reset  
7.2.1 Power-Up Sequence  
An active low on terminal 6 (RESET) while MCLK is running resets the internal microcontroller and DSPs. RESET  
synchronizes internally and can be asserted asynchronously or with the simple RC circuit in Figure 7−1. On reset,  
2
SCL and SDA go to a high-impedance state. If the I C address is set to 68h, approximately 400 µs after RESET  
2
returns to a 1, the device sends a one-byte query via I C to look for an EEPROM. If an EEPROM is found, the TAS3002  
2
2
becomes an I C master; otherwise, it becomes an I C slave. When using address 68h in the slave mode, an external  
master must wait until after the EEPROM query or else bus contention and improper operation occur.  
2
I C address x6Ah does not query the bus for an EEPROM. The address for the EEPROM is A0h.  
7.2.2 Reset  
The TAS3002 device has an asynchronous reset terminal (RESET). This reset is synchronized with various clocks  
used in this device to generate a synchronous internal reset. Upon reset, the TAS3002 device goes through the  
following process:  
Clears all the RAM memory content  
7−1  
 
Clears all the registers in the circuits  
Purges the codec  
Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA) low  
Initializes the equalization parameters to AllPass filters  
2
Sets the digital audio interface to the I S 18-bit mode  
Sets the bass/treble to 0 dB  
Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog-in  
Sets the volume to –40 dB  
Turns off all enhancement features (DRCE, etc.)  
2
Reads the I C address. If the address is 68h, the device reads its EEPROM. It is possible to load the  
user-defined bass/treble data and break points (optional). If there is no data, the device loads default  
bass/treble delta and break points from ROM.  
2
If the address is 6Ah, the device puts the I C interface in slave mode and waits for input.  
7.2.3 Reset Circuit  
Because the TAS3002 device has an internal power-on reset (POR), in many cases, additional components are not  
needed to reset the device. It resets internally at approximately 80% of V  
.
DD  
In the case where the system power supplies are slow in reaching their final voltage or where there is a difference  
in the time the system power supplies take to become stable, the TAS3002 reset can be delayed by a simple RC  
circuit.  
DV  
DD  
10 kΩ  
TAS3002  
6
RESET  
0.1 µF  
DV  
SS  
Figure 7−1. TAS3002 Reset Circuit  
The reset delay for the above circuit can be calculated by the simple equation:  
t
= 0.8RC + 400 µs  
rd  
Where:  
t
= The delay before the TAS3002 device comes out of reset  
rd  
C = Value of the capacitance from RESET (pin 6) to DV  
SS  
R = Value of the resistance from RESET (pin 6) to DV  
DD  
The circuit described in Figure 7−1 delays the start-up of the TAS3002 device approximately 1.2 ms.  
When it is necessary to control the reset of the TAS3002 device with an external device, such as a microcontroller,  
RESET (pin 6) can be treated as a logic signal. It then brings the device out of reset when the voltage on RESET  
reaches V /2.  
DD  
7.2.4 Fast Load Mode  
While in fast load mode—FL bit (bit 7 of main control register 1) = 0—it is possible to update the parametric  
equalization without any audio processing delay. The audio processor pauses while the RAM is updated in this mode.  
7−2  
 
Bass and treble cannot download in this mode. Mixer1 and Mixer2 registers can download in this mode or normal  
mode (FL bit = 0).  
Once the download is complete, the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1  
(MCR1). This puts the TAS3002 device into normal mode.  
7.2.5 Codec Reset  
During initialization, the output of the codec is disabled. Throughout reset and initialization, the output of the DAC is  
muted to prevent extraneous noise being sent to the system output.  
Data from the ADC and other internal processing is purged so that when reset/initialization is complete, only valid  
inputs are sent to the system output.  
7.3 Power-Down Mode  
The TAS3002 device has an asynchronous power-down mode. In the power-down mode, the internal control  
registers and equalization programming of the device are stored in the device.  
To enter power-down mode:  
1. Assert the power-down control signal (1)  
2. Set the serial audio input clocks to 0  
The TAS3002 device goes into power-down mode.  
To exit the power-down mode:  
1. Assert RESET (logic 0)  
2. Restart the serial audio clocks  
3. Wait for a delay of 1.0 ms (to allow the PLL to lock)  
4. Negate the power-down control signal (logic 0)  
5. Negate RESET (logic 1)  
The device then returns to the state it was in before power down (resumes normal operation).  
7−3  
 
7.3.1 Power-Down Timing Sequence  
PWR_DN  
RESET  
MCLK  
SCLK  
LRCLK  
SDATA  
Power-Down Mode  
Normal Operation  
1 ms  
Figure 7−2. Power-Down Timing Sequence  
In power-down mode, the TAS3002 device typically consumes less than 1 mA.  
7.4 Test Mode  
Terminal 9 (TEST) is tied low in normal operation. This function is reserved for factory test and must not be asserted.  
7.5 Internal Interface  
Figure 7−3 shows the flow chart of the interface between the microcontroller and its peripheral blocks.  
7.6 GPI Terminal Programming  
2
During initialization, the microcontroller fetches a control byte from its EEPROM or receives a command from I C.  
7.6.1 GPI Interface  
The six GPI terminals are programmed to operate as indicated in Table 7−1.  
7−4  
 
Table 7−1. GPI Terminal Programming  
GPI5  
GPI4  
GPI3  
GPI2  
GPI1  
GPI0  
VOL_UP, +1 dB  
VOL_DN, −1 dB  
BASS_UP, +1 dB  
BASS_DN, −1 dB  
TREB_UP, +1 dB  
TREB_DN, −1 dB  
Shift 1  
x
x
x
x
x
x
x
x
x
Mute  
EQ1  
x
EQ2  
x
x
EQ3  
x
x
EQ4  
x
EQ5  
x
Shift 2  
NOTE: x = Logic low  
Initially (after reset), the TAS3002 GPI is set to control volume, bass, and treble. Simultaneously setting GPI bits 1  
and 5 low for 1 second changes the function of the GPI terminals to control mute and equalization.  
To return to volume, bass, and treble control, simultaneously set GPI terminals 2 and 3 low for 1 second.  
2
When a GPI terminal is activated, the TAS3002 device echoes its function over I C to a TAS3001 device mapped  
to address 6Ah. Therefore, a system with two audio equalization chips can be implemented without the need for a  
microcontroller.  
7.6.2 GPI Architecture  
The GPI provides simple but flexible input port to activate the input parameters. Each terminal input is an active logic  
low.  
7−5  
 
Start  
Power Up  
Restore Volume  
and MCR  
Initialize Default  
EEPROM  
Initialize TAS3002  
TAS3001  
Load Parameters  
and Coefficients  
to DSP  
Slave Write  
Volume/Bass/Treble Up/Down  
Echo to TAS3001  
GPI  
Switch BQ Set  
Save Volume, Mute  
Save PWR_DN  
Stop PLL  
Power Down  
Stop  
DRC_OFF  
DRC  
Figure 7−3. Internal Interface Flow Chart  
7−6  
 
7.7 External EEPROM Memory Maps  
Table 7−2 through Table 7−5 show the 512-byte and 2048-byte EEPROM memory maps.  
Table 7−2. 512-Byte EEPROM Memory Map 2.0 Channels  
ADDRESS  
000h  
BYTE NUMBER  
FUNCTION  
1
1
Signature (2Ah)  
ID byte = 0000 0000  
MCR  
001h  
002h  
1
003h−00Bh  
00Ch−014h  
015h−01Ah  
01Bh  
9
Mixer left gain  
Mixer right gain  
9
2
DRC (ratio, threshold, energyα, attackα, decayα)  
1
Bass  
01Ch  
1
Treble  
01Dh−022h  
031h−03Fh  
040h−04Eh  
04Fh−05Dh  
05Eh−06Ch  
06Dh−07Bh  
07Ch−08Ah  
08Bh−099h  
09Ah  
6
Volume  
Biquad 0  
Biquad 1  
Biquad 2  
15  
15  
15  
15  
15  
15  
15  
1
Biquad 3  
Left channel  
Biquad 4  
Biquad 5  
Biquad 6  
0 dB/bass  
0 dB/treble  
Bass break  
Treble break  
Bass delta  
Treble delta  
Bass set point  
Treble set point  
Biquad 0  
09Bh  
1
09Ch−0A1h  
0A2h−0A7h  
0A8h−110h  
111h−179h  
17Ah−17Fh  
180h−185h  
186h−194h  
195h−1A3h  
1A4h−1B2h  
1B3h−1C1h  
1C2h−1D0h  
1D1h−1DFh  
1E0h−1EEh  
6
6
105  
105  
6
6
15  
15  
15  
15  
15  
15  
15  
Biquad 1  
Biquad 2  
Biquad 3  
Right channel  
Biquad 4  
Biquad 5  
Biquad 6  
2
NOTE: Bytes are in the same order as they appear in the I C register map. The EEPROM address is A0h.  
7−7  
 
Table 7−3. 512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001)  
ADDRESS  
000h  
BYTE NUMBER  
FUNCTION  
1
1
Signature (2Ah)  
001h  
ID byte = 0000 0011  
TAS3002  
002h  
1
9
MCR  
003h−00Bh  
00Ch−014h  
015h−01Ah  
01Bh  
Mixer left gain  
9
Mixer right gain  
6
DRC (ratio, threshold, energyα, attackα, decayα)  
1
Bass  
01Ch  
1
Treble  
01Dh−022h  
031h−03Fh  
040h−04Eh  
04Fh−05Dh  
05Eh−06Ch  
06Dh−07Bh  
07Ch−08Ah  
08Bh−099h  
09Ah  
6
Volume  
15  
15  
15  
15  
15  
15  
15  
1
Biquad 0  
Biquad 1  
Biquad 2  
TAS3002  
right and left  
channel  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
0 dB/bass  
09Bh  
1
0 dB/treble  
09Ch−0A1h  
0A2h−0A7h  
0A8h−110h  
111h−179h  
17Ah−17Fh  
180h−185h  
186h−194h  
195h−1A3h  
1A4h−1B2h  
1B3h−1C1h  
1C2h−1D0h  
1D1h−1DFh  
1E0h−1EEh  
6
Bass break  
6
Treble break  
105  
105  
6
Bass delta  
Treble delta  
Bass set point  
6
Treble set point  
15  
15  
15  
15  
15  
15  
15  
Biquad 0  
Biquad 1  
Biquad 2  
TAS3001  
right and left  
channel  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
TAS3001  
1EFh  
1F0h−1F2h  
1F3h−1F5h  
1F6h−1F7h  
1F8h  
1
3
3
2
1
1
6
MCR  
SDIN1 gain  
SDIN2 gain  
DRC (ratio, threshold, energyα, attackα, decayα)  
Bass  
Treble  
Volume  
1F9h  
1FAh−1FFh  
NOTE: In this mode, the TAS3002 and the TAS3001 devices both use the same equalization coefficients for their right and left channels.  
2
Bytes are in the same order as they appear in the I C register map. The EEPROM address is A0h.  
7−8  
 
Table 7−4. 2048-Byte EEPROM Memory Map—2.0 Speakers With Multiple Equalizations  
TAS3002 ADDRESS  
LEFT BIQUAD  
NUMBER  
OF BYTES  
TAS3002 ADDRESS  
RIGHT BIQUAD  
FUNCTION  
CATEGORY  
TAS3001  
000h  
1
1
Signature (2Ah)  
001h  
1
0
0
0
0
0
1
0
002h  
1
MCR  
1EFh  
003h−00Bh  
00Ch−014h  
015h−019h  
01Ah  
9/3  
9/3  
6/2  
1
Mixer left gain  
Mixer right gain  
1F0h−1F2h  
1F3h−1F5h  
1F6h−1F7h  
1F8h  
DRC (ratio, threshold, energyα, attackα, decayα)  
Bass  
Treble  
Volume  
01Bh  
1
1F9h  
01Ch−021h  
031h−03Fh  
040h−04Eh  
04Fh−05Dh  
05Eh−06Ch  
06Dh−07Bh  
07Ch−08Ah  
08Bh−099h  
09Ah−185h  
200h−20Eh  
20Fh−21Dh  
21Eh−22Ch  
22Dh−23Bh  
23Ch−24Ah  
24Bh−259h  
25Ah−268h  
269h−277h  
278h−286h  
287h−295h  
296h−2A4h  
2A5h−2B3h  
2B4h−2C2h  
2C3h−2D1h  
2D2h−2E0h  
2E1h−2EFh  
2F0h−2FEh  
2FFh−30Dh  
30Eh−31Ch  
31Dh−32Bh  
32Ch−33Ah  
33Bh−349h  
34Ah−358h  
359h−367h  
368h−376h  
377h−385h  
386h−394h  
395h−3A3h  
6
1FAh−1FFh  
186h−194h  
195h−1A3h  
1A4h−1B2h  
1B3h−1C1h  
1C2h−1D0h  
1D1h−1DFh  
1E0h−1EEh  
15  
15  
15  
15  
15  
15  
15  
236  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
Biquad 0  
3A4h−3B2h  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
3B3h−3C1h  
3C2h−3D0h  
3D1h−3DFh  
3E0h−3EEh  
3EFh−3FDh  
3FEh−40Ch  
Set 0  
Bass treble table  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
40Dh−41Bh  
41Ch−42Ah  
42Bh−439h  
43Ah−448h  
449h−457h  
458h−466h  
467h−475h  
476h−484h  
485h−493h  
494h−4A2h  
4A3h−4B1h  
4B2h−4C0h  
4C1h−4CFh  
4D0h−4DEh  
4DFh−4EDh  
4EEh−4FCh  
4FDh−50Bh  
50Ch−51Ah  
51Bh−529h  
52Ah−538h  
539h−547h  
548h−556h  
557h−565h  
566h−574h  
575h−583h  
584h−592h  
593h−5A1h  
5A2h−5B0h  
5B1h−5BFh  
5C0h−5CEh  
5CFh−5DDh  
5DEh−5ECh  
5EDh−5FBh  
5FCh−60Ah  
60Bh−619h  
61Ah−628h  
629h−637h  
638h−646h  
647h−655h  
656h−664h  
665h−673h  
674h−682h  
683h−691h  
692h−6A0h  
6A1h−6AFh  
6B0h−6BEh  
6BFh−6CDh  
6CEh−6DCh  
6DDh−6EBh  
6ECh−6FAh  
6FBh−709h  
70Ah−718h  
719h−727h  
728h−736h  
737h−745h  
746h−754h  
Set 1  
Set 2  
Set 3  
Set 4  
2
NOTE: Bytes are in the same order as they appear in the I C register map. The EEPROM address is A0h.  
7−9  
 
Table 7−5. 2048-Byte EEPROM Memory Map—2.1 Speakers With Multiple Equalizations  
NUMBER  
OF BYTES  
TAS3001 ADDRESS TAS3001 ADDRESS  
LEFT CHANNEL RIGHT CHANNEL  
TAS3002 ADDRESS  
FUNCTION  
CATEGORY  
000h  
1
1
Signature (2Ah)  
001h  
1
0
0
0
0
0
0
1
002h  
1
MCR  
1EFh  
003h−00Bh  
00Ch−014h  
015h−019h  
01Ah  
9/3  
9/3  
6/2  
1
Mixer left gain  
Mixer right gain  
1F0h−1F2h  
1F3h−1F5h  
1F6h−1F7h  
1F8h  
DRC (ratio, threshold, energyα, attackα, decayα)  
Bass  
Treble  
Volume  
01Bh  
1
1F9h  
01Ch−021h  
031h−03Fh  
040h−04Eh  
04Fh−05Dh  
05Eh−06Ch  
06Dh−07Bh  
07Ch−08Ah  
08Bh−099h  
09Ah−185h  
200h−20Eh  
20Fh−21Dh  
21Eh−22Ch  
22Dh−23Bh  
23Ch−24Ah  
24Bh−259h  
25Ah−268h  
269h−277h  
278h−286h  
287h−295h  
296h−2A4h  
2A5h−2B3h  
2B4h−2C2h  
2C3h−2D1h  
2D2h−2E0h  
2E1h−2EFh  
2F0h−2FEh  
2FFh−30Dh  
30Eh−31Ch  
31Dh−32Bh  
32Ch−33Ah  
33Bh−349h  
34Ah−358h  
359h−367h  
368h−376h  
377h−385h  
386h−394h  
395h−3A3h  
6
1FAh−1FFh  
3A4h−3B2h  
3B3h−3C1h  
3C2h−3D0h  
3D1h−3DFh  
3E0h−3EEh  
3EFh−3FDh  
3FEh−40Ch  
15  
15  
15  
15  
15  
15  
15  
236  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
15  
Biquad 0  
186h−194h  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
195h−1A3h  
1A4h−1B2h  
1B3h−1C1h  
1C2h−1D0h  
1D1h−1DFh  
1E0h−1EEh  
Set 0  
Bass treble table  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
Biquad 0  
Biquad 1  
Biquad 2  
Biquad 3  
Biquad 4  
Biquad 5  
Biquad 6  
5B1h−5BFh  
5C0h−5CEh  
5CFh−5DDh  
5DEh−5ECh  
5EDh−5FBh  
5FCh−60Ah  
60Bh−619h  
61Ah−628h  
629h−637h  
638h−646h  
647h−655h  
656h−664h  
665h−673h  
674h−682h  
683h−691h  
692h−6A0h  
6A1h−6AFh  
6B0h−6BEh  
6BFh−6CDh  
6CEh−6DCh  
6DDh−6EBh  
6ECh−6FAh  
6FBh−709h  
70Ah−718h  
719h−727h  
728h−736h  
737h−745h  
746h−754h  
40Dh−41Bh  
41Ch−42Ah  
42Bh−439h  
43Ah−448h  
449h−457h  
458h−466h  
467h−475h  
476h−484h  
485h−493h  
494h−4A2h  
4A3h−4B1h  
4B2h−4C0h  
4C1h−4CFh  
4D0h−4DEh  
4DFh−4EDh  
4EEh−4FCh  
4FDh−50Bh  
50Ch−51Ah  
51Bh−529h  
52Ah−538h  
539h−547h  
548h−556h  
557h−565h  
566h−574h  
575h−583h  
584h−592h  
593h−5A1h  
5A2h−5B0h  
Set 1  
Set 2  
Set 3  
Set 4  
2
NOTE: Bytes are in the same order as they appear in the I C register map. The EEPROM address is A0h.  
7−10  
 
8 Electrical Characteristics  
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges  
Supply voltage range: AV  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.6 V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.6 V  
DD  
DD  
DV  
Analog input voltage range: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to AV  
Digital input voltage range: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to DV  
+ 0.3 V  
+ 0.3 V  
DD  
DD  
Operating free-air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +122°C  
Lead temperature from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +97.8°C  
Electrostatic discharge (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V  
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.  
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: Human body model per Method 3015.2 of MIL-STD-833B.  
8.2 Recommended Operating Conditions  
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V  
A
DD  
DD  
Voltages at analog inputs and outputs and at AV  
are with respect to ground.  
DD  
MIN  
3.0  
NOM MAX  
UNIT  
V
Supply voltage, AV  
DD  
3.3  
3.3  
34  
3.6  
3.6  
Supply voltage, DV  
DD  
3.0  
V
Operating  
mA  
µA  
Supply current, analog  
Supply current, digital  
Power down (see Note 2)  
Operating  
88  
47  
mA  
µA  
Power down (see Note 2)  
Operating  
942  
267  
mW  
mW  
Power dissipation  
Power down (see Note 2)  
3.5  
NOTE 2: If the clocks are turned off.  
8.3 Static Digital Specifications  
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V  
A
DD  
DD  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
3.6  
UNIT  
V
V
V
V
V
High-level input voltage  
Low-level input voltage  
High-level output voltage  
Low-level output voltage  
Input leakage current  
2.0  
−0.3  
2.4  
IH  
0.8  
V
IL  
I
I
= −1 mA  
= +4 mA  
V
OH  
OL  
O
0.4  
10  
50  
V
O
−10  
µA  
pF  
Output load capacitance  
8−1  
 
8.4 ADC Digital Filter  
2
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V, f = 48 kHz, 20-bit I S mode  
A
DD  
DD  
S
All terms characterized by frequency are scaled with the chosen sampling frequency, f . See Figure 8−1 through  
S
Figure 8−4 for performance curves of the ADC digital filter.  
PARAMETER  
ADC decimation filter (LPF) Pass band  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
kHz  
dB  
0.0  
20.0  
Pass band ripple  
Stop band  
0.01  
24.1  
kHz  
dB  
Stop band attenuation  
Group delay  
80  
720  
0.87  
1.23  
µs  
ADC high-pass filter (HPF)  
Pass band (−3 dB)  
Deviation from linear phase  
Hz  
20 Hz to 20 kHz  
degrees  
50  
0
−50  
−100  
−150  
−200  
0
2 f  
s
4 f  
s
6 f  
s
8 f  
s
10 f  
12 f  
s
s
f − Frequency − Hz  
Figure 8−1. ADC Digital Filter Characteristics  
0
−20  
−40  
−60  
−80  
−100  
0
0.2 f  
0.4 f  
0.6 f  
0.8 f  
1 f  
s
s
s
s
s
f − Frequency − Hz  
Figure 8−2. ADC Digital Filter Stop-Band Characteristics  
8−2  
 
0.008  
0.006  
0.004  
0.002  
0
−0.002  
0
0.1 f  
0.2 f  
0.3 f  
0.4 f  
0.5 f  
s
s
s
s
s
f − Frequency − Hz  
Figure 8−3. ADC Digital Filter Pass-Band Characteristics  
0.2  
0
−0.2  
−0.4  
−0.6  
−0.8  
−1  
0
1 f  
s
2 f  
s
3 f  
s
4 f  
s
f − Frequency − Hz  
Figure 8−4. ADC High-Pass Filter Characteristics  
8.5 Analog-to-Digital Converter  
2
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V, f = 48 kHz, 20-bit I S mode  
A
DD  
DD  
S
All terms characterized by frequency are scaled with the chosen sampling frequency, f .  
S
PARAMETER  
TEST CONDITIONS  
A weighted  
MIN  
TYP  
93  
MAX  
UNIT  
dB  
SNR (EIAJ)  
Dynamic range  
−60 dB, 1 kHz  
88  
dB  
Signal to (noise + distortion) ratio  
Power supply rejection ratio  
Idle channel tone rejection  
Intermodulation distortion  
ADC crosstalk  
−1 dB, 1 kHz, 20 Hz to 20 kHz  
1 kHz (see Note 3)  
82  
dB  
50  
dB  
+110  
−80  
−93  
0.1  
dB  
dB  
dB  
Overall ADC frequency response  
Gain error  
20 Hz to 20 kHz  
dB  
5%  
Gain matching  
0.02  
dB  
NOTE 3: Measured with a 50-mV peak sine curve.  
8−3  
 
8.6 Input Multiplexer  
2
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V, f = 48 kHz, 20-bit I S mode  
A
DD  
DD  
S
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
20  
MAX  
UNIT  
kΩ  
Input impedance  
Crosstalk  
85  
dB  
Full-scale input voltage range  
1.7  
V
PP  
8.7 DAC Interpolation Filter  
2
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V, f = 48 kHz, 20-bit I S mode  
A
DD  
DD  
S
All terms characterized by frequency are scaled with the normal mode sampling frequency, f . See Figure 8−5 and  
S
Figure 8−6 for performance curves of the DAC digital filter.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
kHz  
dB  
Pass band  
0.0  
20.0  
Pass-band ripple  
Stop band  
0.005  
24.1  
kHz  
dB  
Stop-band attenuation  
Group delay  
28.8 kHz to 3 MHz  
75  
700  
µs  
0
−20  
−40  
R
−60  
−80  
−100  
0
f
1 f  
s
2 f  
s
3 f  
s
4 f  
s
5 f  
s
s/2  
f − Frequency − Hz  
Figure 8−5. DAC Filter Overall Frequency Characteristics  
0.1  
0.05  
0
−0.05  
−0.1  
0
0.1 f  
0.2 f  
0.3 f  
0.4 f  
0.5 f  
s
s
s
s
s
f − Frequency − Hz  
Figure 8−6. DAC Digital Filter Pass-Band Ripple Characteristics  
8−4  
 
8.8 Digital-to-Analog Converter  
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V, f = 48 kHz, input = 0 dB-f sine wave at 1 kHz  
A
DD  
DD  
S
S
PARAMETER  
TEST CONDITIONS  
MIN  
94  
TYP  
99  
MAX  
UNIT  
dB  
SNR (EIAJ)  
A weighted  
Dynamic range  
−60 dB, 1 kHz  
92  
96  
dB  
Signal to (noise + distortion) ratio  
Power supply rejection ratio  
Idle channel tone rejection  
Intermodulation distortion  
Frequency response  
0 dB, 1 kHz, 20 Hz to 20 kHz  
1 kHz  
83  
dB  
50  
dB  
+118  
−75  
dB  
dB  
−0.5  
−7.0  
+0.5  
1.4  
dB  
Deviation from linear phase  
DAC crosstalk  
degree  
dB  
−96  
150  
1.9  
Jitter tolerance  
ps  
Full scale, single-ended, output voltage range  
DC offset  
V
PP  
7.0  
mV  
8.9 DAC Output Performance Data  
T = 25°C, AV  
= 3.3 V, DV  
= 3.3 V  
A
DD  
DD  
The output load resistance is connected through a dc blocking capacitor.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
25  
UNIT  
kΩ  
Output load resistance  
Output load capacitance  
10  
pF  
VCOM internal resistance (see Note 4)  
VCOM output CLOAD  
1
10  
1
kΩ  
100  
µF  
VRFILT internal resistance (see Note 5)  
kΩ  
NOTES: 4. VCOM may vary during power down.  
5. VRFILT must never be used as a voltage reference.  
8−5  
 
2
8.10 I C Serial Port Timing Characteristics  
MIN  
0
MAX  
UNIT  
kHz  
µs  
f
t
t
t
t
SCL clock frequency  
100  
(SCL)  
Bus free time between start and stop  
Low period of SCL clock  
High period of SCL clock  
Hold time repeated start  
Setup time repeated start  
Data hold time (See Note 6)  
Data setup time  
4.7  
4.7  
4.0  
4.0  
4.7  
0
(buf)  
µs  
(low)  
µs  
(high)  
h(sta)  
µs  
t
20  
µs  
su(sta)  
t
µs  
h(dat)  
t
250  
ns  
su(dat)  
t
Rise time for SDA and SCL  
Fall time for SDA and SCL  
Setup time for stop condition  
Capacitive load for each bus line  
1000  
300  
ns  
r
t
f
ns  
t
4.0  
µs  
su(sto)  
C
400  
pF  
(b)  
NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of  
SCL.  
P
S
P
SDA  
SCL  
Valid  
t
t
h(dat)  
t
(buf)  
su(sta)  
t
su(dat)  
t
r
t
su(sto)  
Change  
of Data  
Allowed  
Data  
Line  
Stable  
t
t
f
h(sta)  
t
h(sta)  
is measured from the end of t to the beginning of t .  
NOTE: t  
t
(low)  
f
r
is measured from the end of t to the beginning of t .  
(high)  
r
f
2
Figure 8−7. I C Bus Timing  
8−6  
 
9 System Diagrams  
Figure 9−1 and Figure 9−2 show the TAS3002 stereo and 2.1-channel applications, respectively.  
+3.3 V  
DD  
RESET  
Analog Out  
Analog In  
TAS3002  
SPDIF  
or  
2
I S  
USB  
2
I C  
EEPROM  
Master  
B-T-V-EQ Switches  
NOTE: Items such as the PLL network and power supplies are omitted for clarity.  
Figure 9−1. Stereo Application  
9−1  
 
+3.3 V  
DD  
RESET  
Analog Out (To Satellite Amplifiers)  
Analog In  
TAS3002  
SPDIF  
or  
2
I S  
USB  
2
2
I C  
EEPROM  
I S_OUT  
Master  
SDOUT2  
Echoes  
Switches  
on GPIO  
B-T-V-EQ-Sub Vol  
L+R Mix  
2
I C  
Slave  
2
I S  
Analog Out  
PCM1744  
TAS3001  
Address = 6Ah  
NOTE: Items such as the PLL network and power supplies are omitted for clarity.  
Figure 9−2. TAS3002 Device, 2.1 Channels  
9−2  
 
10 Mechanical Information  
The TAS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanical  
dimensions for the PFB package.  
PFB (S-PQFP-G48)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
M
0,08  
36  
25  
37  
24  
48  
13  
0,13 NOM  
1
12  
5,50 TYP  
7,20  
SQ  
Gage Plane  
6,80  
9,20  
SQ  
8,80  
0,25  
0,05 MIN  
0°ā7°  
1,05  
0,95  
0,75  
0,45  
Seating Plane  
0,08  
1,20 MAX  
4073176/B 10/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
10−1  
 
10−2  
 

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