Texas Instruments Stereo Amplifier TAS5066PAG User Manual

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User’s Guide  
March 2004  
Digital Audio and Video Products  
SLEU052  
 
EVM IMPORTANT NOTICE  
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:  
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION  
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided  
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective  
considerations, including product safety measures typically found in the end product incorporating the goods.  
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic  
compatibility and therefore may not meet the technical requirements of the directive.  
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned  
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE  
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,  
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY  
PARTICULAR PURPOSE.  
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user  
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products  
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction  
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic  
discharge.  
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE  
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.  
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not  
exclusive.  
TI assumes no liability for applications assistance, customer product design, software performance, or  
infringement of patents or services described herein.  
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM  
User’s Guide prior to handling the product. This notice contains important safety information about temperatures  
and voltages. For further safety concerns, please contact the TI application engineer.  
Persons handling the product must have electronics training and observe good laboratory practice standards.  
No license is granted under any patent right or other intellectual property right of TI covering or relating to any  
machine, process, or combination in which such TI products or services might be or are used.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2004, Texas Instruments Incorporated  
 
EVM WARNINGS AND RESTRICTIONS  
It is important to operate this EVM within the input voltage range of xxx V and the output  
voltage range of xxx V and xxx V.  
Exceeding the specified input range may cause unexpected operation and/or irreversible  
damage to the EVM. If there are questions concerning the input range, please contact a TI  
field representative prior to connecting the input power.  
Applying loads outside of the specified output range may result in unintended operation and/or  
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to  
connecting any load to the EVM output. If there is uncertainty as to the load specification,  
please contact a TI field representative.  
During normal operation, some circuit components may have case temperatures greater than  
xxx°C. The EVM is designed to operate properly with certain components above xxx°C as  
long as the input and output ranges are maintained. These components include but are not  
limited to linear regulators, switching transistors, pass transistors, and current sense  
resistors. These types of devices can be identified using the EVM schematic located in the  
EVM User’s Guide. When placing measurement probes near these devices during operation,  
please be aware that these devices may be very warm to the touch.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2004, Texas Instruments Incorporated  
 
Preface  
Read This First  
About This Manual  
This manual describes the operation of the TAS5066-5111D6EVM evaluation  
module from Texas Instruments.  
How to Use This Manual  
This document contains the following chapters:  
- Chapter 1 — Overview  
- Chapter 2 — System Interfaces  
- Chapter 3 — Protection  
Information about Cautions and Warnings  
This document may contain cautions and warnings.  
This is an example of a caution statement.  
A caution statement describes a situation that could potentially  
damage your software or equipment.  
This is an example of a warning statement.  
A warning statement describes a situation that could potentially  
cause harm to you.  
The information in a caution or a warning is provided for your protection.  
Please read each caution and warning carefully.  
v
 
Trademarks  
Related Documentation from Texas Instruments  
The following table contains a list of data manuals that have detailed descrip-  
tions of the integrated circuits used in the design of the  
TAS5066−5111D6EVM. The data manuals can be obtained at the URL  
Part Number  
Literature Number  
TAS5066PAG  
SLES089  
TAS5111DAD  
SN74LVC1G08  
SN74LVC1G126  
LMV331I  
SLES049  
SCES217O  
SCES224J  
SLCS136K  
SLVS297I  
SLVS180B  
SLVS219B  
LM317M  
TPS76433  
TPS3801K33  
Additional Documentation  
- TAS5066−5111D6EVM Application Report − SLEA033  
- PC Configuration Tool for TAS50XX (DAS TCT 50xx – version 3.1 or later)  
- General Application Notes  
FCC Warning  
This equipment is intended for use in a laboratory test environment only. It gen-  
erates, uses, and can radiate radio frequency energy and has not been tested  
for compliance with the limits of computing devices pursuant to subpart J of  
part 15 of FCC rules, which are designed to provide reasonable protection  
against radio frequency interference. Operation of this equipment in other en-  
vironments may cause interference with radio communications, in which case  
the user at his own expense will be required to take whatever measures may  
be required to correct this interference.  
Trademarks  
TM  
TM  
TI, Equibit  
and PurePath Digital  
are trademarks of Texas Instruments.  
vi  
 
Contents  
1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
1.1  
1.2  
TAS5066-5111D6EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
PCB Key Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
PSU Interface (J901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
PSU Control Interface (J902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
Loudspeaker Connectors (J100 − J600) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
Control Interface (J50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
Digital Audio Interface (J51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7  
PWM Timing, Interchannel Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8  
3
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
3.1  
3.2  
Short Circuit Protection and Fault Reporting Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
Device Fault Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
vii  
 
Figures  
1−1  
1−2  
2−1  
2−2  
2−3  
2−4  
Complete PurePath Digital System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
Physical Structure for the TAS5066-5111D6EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
Recommended Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
J901 and J903 Pin Numbers (PCB Connector Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
J902 Pin Numbers (PCB Connector Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
J100 − J600 Pin Numbers (PCB Connector Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
Tables  
2−1  
2−2  
2−3  
2−4  
2−5  
2−6  
2−7  
2−8  
2−9  
3−1  
Recommended Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
J901 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
J903 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
J902 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
J100− J600 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
J50 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
J51 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7  
Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7  
Recommended Interchannel Delay Register Values (based on EVM designs) . . . . . . . . . 2-8  
TAS5111 Error Signal Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
viii  
 
Chapter 1  
Overview  
The TAS5066−5111D6EVM PurePath Digitalt customer evaluation module  
demonstrates two integrated circuits TAS5066 and TAS5111DAD from Texas  
Instruments (TI).  
The TAS5066 is a high-performance 24-bit six-channel digital pulse width  
TM  
modulator (PWM) based on Equibit  
technology. The TAS5066 has a wide  
variety of serial input (I@S) options including right justified, left justified, and  
DSP data formats. It accepts I@S data with sample rates up to 192 kHz.  
TAS5111 is a high-performance digital amplifier power stage designed to drive  
a 4-Ohm loudspeaker up to 85 W. It contains integrated gate-drivers, four  
matched and electrically isolated enhancement-mode N-channel power  
DMOS transistors and protection / fault-reporting circuitry.  
The TAS5066−5111D6EVM, together with a TI input board, is a complete digi-  
tal audio amplifier system that includes digital input (S/PDIF), analog input, in-  
terface to PC, digital volume control, and failure protection. The system was  
design for home theater applications such as DVD minicomponent systems,  
home theater in a box (HTIB), DVD receiver, A/V receiver, or TV sets.  
Topic  
Page  
1.1 TAS5066-5111D6EVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
1.2 PCB Key Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
1-1  
 
TAS5066-5111D6EVM Features  
1.1 TAS5066-5111D6EVM Features  
- 6-channel PurePath Digitalt evaluation module  
- Self-contained protection system (short circuit and thermal)  
2
2
- Standard I S and I C/control connector for TI input board  
- Double-sided plated-through PCB layout  
Figure 1−1. Complete PurePath DigitalE System  
Power  
supply  
Subwoofer  
line out  
6 channel  
analog input  
Control interface  
TAS5066–5111D6EVM  
module  
2
PC interface  
I C bus  
Optical and  
coaxial  
2
I S bus  
S/PDIF input  
Example  
TI input–PC board  
1-2  
 
PCB Key Map  
1.2 PCB Key Map  
The physical structure for the TAS5066−5111D6EVM is illustrated in the fol-  
lowing figure.  
Figure 1−2. Physical Structure for the TAS5066-5111D6EVM  
J903  
H-Bridge  
PSU  
J902  
PSU CONTROL  
J100  
J200  
J300  
J400  
J500  
J600  
TAS5066  
J50  
CONTROL INTERFACE  
J51  
AUDIO INTERFACE  
Overview  
1-3  
 
1-4  
 
Chapter 2  
System Interfaces  
This chapter describes the TAS5066−5111D6EVM board in regards to power  
supply (PSU) and system interfaces.  
Topic  
Page  
2.1 PSU Interface (J901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 PSU Control Interface (J902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
2.3 Loudspeaker Connectors (J100 − J600) . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
2.4 Control Interface (J50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
2.5 Digital Audio Interface (J51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7  
2.6 PWM Timing, Interchannel Delay Registers . . . . . . . . . . . . . . . . . . . . . . 2-8  
2-1  
 
PSU Interface (J901)  
2.1 PSU Interface (J901)  
The TAS5066−5111D6EVM module must be powered from one or two exter-  
nal regulated power supplies. High audio performance requires a stabilized  
output stage power supply with low ripple voltage and low output impedance.  
Note:  
The length of power supply cable must be minimized. Increasing length of  
PSU cable is equal to increasing the distortion for the amplifier at high output  
levels and low frequencies.  
Maximum output stage supply voltage depends of the speaker load resist-  
ance. Please check the recommended maximum supply voltage in the  
TAS5111 datasheet.  
Table 2−1.Recommended Power Supplies  
Description  
Voltage Limitations  
Current  
(4-W Load)  
Recommendations  
System power supply  
15 to 20 V  
0 to 29.5 V  
0.25 A  
Output power stage supply  
5.5 A  
The rated current corresponds to 2-channel full scale (70 W each) or 6-channel 1/8 scale (9 W  
each), which most likely is adequate for a standard 6-channel amplifier design.  
Figure 2−1 shows the recommended TAS5111 power-up sequence. For prop-  
er TAS5111 operation the RESET signal must be kept low during power-up.  
RESET is pulled low during power-up for 200 ms by the on-board reset genera-  
tor (U903).  
Figure 2−1. Recommended Power-Up Sequence  
System power supply  
Output stage power supply  
RESET  
>1 ms  
2-2  
 
PSU Interface (J901)  
Figure 2−2. J901 and J903 Pin Numbers (PCB Connector Top View)  
4
3
2
1
Table 2−2.J901 Pin Description  
Pin Number Net-Name at Schematics  
Description  
1
2
3
4
V-HBRIDGE  
Output stage power supply  
System power supply  
Ground  
GND  
GND  
Ground  
Table 2−3.J903 Pin Description  
Pin Number Net-Name at Schematics  
Description  
Output stage power supply  
Output stage power supply  
Ground  
1
2
3
4
V-HBRIDGE  
V-HBRIDGE  
GND  
GND  
Ground  
Note: Optional, use to decrease impedance to achieve better performance.  
System Interfaces  
2-3  
 
PSU Control Interface (J902)  
2.2 PSU Control Interface (J902)  
This interface is used for on-board sensing of output supply voltage and for  
power supply volume control (PSCV) signal.  
Figure 2−3. J902 Pin Numbers (PCB Connector Top View)  
5
4
3
2
1
Table 2−4.J902 Pin Description  
Pin Number Net-Name at Schematics  
Description  
1
2
3
4
5
NOT USED  
V-HBRIDGE  
GND  
Sense of output supply voltage  
Ground  
RESET  
System reset (bi-directional)  
Power supply volume control  
PSVC  
2-4  
 
Loudspeaker Connectors (J100 − J600)  
2.3 Loudspeaker Connectors (J100 − J600)  
Both positive and negative speaker outputs are floating and may  
not be connected to ground (e.g., through an oscilloscope).  
Figure 2−4. J100 − J600 Pin Numbers (PCB Connector Top View)  
2
1
Table 2−5.J100− J600 Pin Description  
Pin Number Net-Name at Schematics  
Description  
Speaker negative output  
Speaker positive output  
1
2
OUT−1  
OUT−2  
System Interfaces  
2-5  
 
Control Interface (J50)  
2.4 Control Interface (J50)  
This interface connects the TAS5066-5111D6EVM board to a TI input board.  
Table 2−6.J50 Pin Description  
Pin Number Net-Name at Schematics  
Description  
1
2
3
4
GND  
PSVC  
GND  
Ground  
Power supply volume control from (mC) input board  
Ground  
RESET  
System reset (bi-directional). Activate MUTE before RESET for  
quiet reset.  
5
6
7
ERR-RCVY  
MUTE  
Error recovery or soft reset provides click and pop free reset,  
without resetting I C volume register settings.  
2
Ramp volume from any setting to noiseless soft mute. Mute can  
2
also be activated by I C.  
PDN  
Power down. TAS5066 enters the power down state when acti-  
vated.  
8, 9  
10  
RESERVED  
SDA  
2
I C data clock  
11  
GND  
Ground  
2
12  
SCL  
I C bit clock  
13, 14  
15  
RESERVED  
DBSPD  
Double speed mode. Double speed active when high and inac-  
tive when low  
16  
CLIP_MODULATOR  
Clipping indicator from TAS5066. Indicates 0dB level with low  
signal  
17  
18, 19  
20  
GND  
Ground  
RESERVED  
SHUTDOWN1  
Shutdown error reporting for all channels. Activated if TAS5111  
has high current or high temperature for approximately 100 ms.  
See Chapter 3, Protection.  
21  
22  
RESERVED  
TEMP_WARNING  
Temperature warning. Activated with low signal if one or more  
TAS5111 has reached temperature warning level.  
23, 24  
25, 26  
27−30  
31, 32  
33, 34  
RESERVED  
GND  
Ground  
RESERVED  
GND  
Ground  
+5V  
+5-Vdc power supply (output)  
2-6  
 
Digital Audio Interface (J51)  
2.5 Digital Audio Interface (J51)  
The digital audio interface contains digital audio signal data (I2S), clocks etc.  
Please see the TAS5066 data manual for signal timing and details not ex-  
plained in this document.  
Table 2−7.J51 Pin Description  
Pin Number Net-Name at Schematics  
Description  
1
2
GND  
Ground  
MCLK  
Master clock input. Low jitter system clock for PWM generation  
and reclocking.  
Ground connection from source to TAS5066 must be a low im-  
pedance connection.  
3
4
GND  
SDIN1  
SDIN2  
SDIN3  
Ground  
I2S data 1, channels 1 and 2  
I2S data 2, channels 3 and 4  
I2S data 3, channels 5 and 6  
Reserved  
5
6
7−9  
10  
11  
12  
13  
14  
15  
16  
GND  
SCLK  
GND  
LRCLK  
GND  
Ground  
I2S bit clock  
Ground  
I2S left-right clock  
Ground  
Reserved  
GND  
Ground  
Table 2−8.Clock Rates  
Speed  
TAS5066 System  
Sample  
LRCLK  
SCLK (64xF )  
S
MCLK  
Control Register Frequency  
0 (x02h)  
(F )  
S
Normal speed  
D7 = 0  
D6 = 0  
32 kHz  
44.1 kHz  
48 kHz  
64 kHz  
88 kHz  
96 kHz  
176 kHz  
192 kHz  
32.0 kHz  
44.1 kHz  
48.0 kHz  
64.0 kHz  
88.2 kHz  
96.0 kHz  
176.4 kHz  
192.0 kHz  
2.0480 MHz  
2.8224 MHz  
3.0720 MHz  
4.0960 MHz  
5.6448 MHz  
6.1440 MHz  
11.2896 MHz  
12.2880 MHz  
8.1920 MHz  
11.2896 MHz  
12.2880 MHz  
16.3840 MHz  
22.5792 MHz  
24.5760 MHz  
22.5790 MHz  
24.5760 MHz  
MCLK = 256xF  
S
Double speed  
D7 = 0  
D6 = 1  
MCLK = 256xF  
S
Quad speed  
D7 = 1  
D6 = 0  
MCLK = 128xF  
S
System Interfaces  
2-7  
 
PWM Timing, Interchannel Delay Registers  
2.6 PWM Timing, Interchannel Delay Registers  
For maximum performance, the PWM timing must be optimized for the specific  
configuration and PCB layout. The default values in TAS5066 is properly not  
optimal in many designs and therefore the interchannel delays must be pro-  
grammed by I2C to the TAS5066 at startup and after every system reset.  
Table 2−9.Recommended Interchannel Delay Register Values (based on EVM designs)  
Register Description  
Register  
Address  
Value (hex)  
Inter−Channel Delay Channel 1  
0x0C  
0x0D  
0x0E  
0x0F  
0x10  
0x11  
0x01  
0x49  
0x91  
0xD9  
0x21  
0x69  
Inter−Channel Delay Channel 2  
Inter−Channel Delay Channel 3  
Inter−Channel Delay Channel 4  
Inter−Channel Delay Channel 5  
Inter−Channel Delay Channel 6  
2-8  
 
Chapter 3  
Protection  
This chapter describes the short circuit protection and fault reporting circuitry  
of the TAS5111 device.  
Topic  
Page  
3.1 Short Circuit Protection and Fault Reporting Circuitry . . . . . . . . . . . 3-2  
3.2 Device Fault Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3-1  
 
Short Circuit Protection and Fault Reporting Circuitry  
3.1 Short Circuit Protection and Fault Reporting Circuitry  
TAS5111 is a self-protecting device that provides device fault reporting (includ-  
ing high-temperature protection and short circuit protection). TAS5111 is con-  
figured in back-end auto-recovery mode and therefore resets automatically af-  
ter all errors (M1, M2 and M3 is set low). This means that the device will re-start  
itself after a error occasion and report shortly through the SHUTDOWN error  
signals.  
3.2 Device Fault Reporting  
The OTW and SD outputs from TAS5111 indicate fault conditions. Please refer  
to the TAS5111 data manual for a description of these pins.  
Table 3−1.TAS5111 Error Signal Decoding  
OTW  
SD  
Device Condition  
High temperature error and/or high current error  
High temperature warning  
0
0
0
1
1
1
0
1
Under voltage lockout or high current error  
Normal operation, no errors/warnings  
The temperature warning (OTW) signals at the TAS5066−5111D6EVM board  
are wired-OR to one temperature warning signal (TEMP_WARNING – pin 22  
in control interface connector). Shutdown signals (SD) are wired-OR to one  
shutdown signal (SHUTDOWN – pin 20 in control interface connector). The  
shutdown signals together with the temperature warning signal will give infor-  
mation on the chip state information as described in the previous table. Device  
fault reporting outputs are open-drain outputs.  
3-2  
 

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